The present invention relates to a storage array for use in a computer system.
In a computer system, instructions are typically fetched from a program memory, decoded and supplied to an execution unit where they are executed to run the program stored in the program memory. According to a novel design of computer system developed by the applicants, a number of different instruction modes are supported. To support these modes, data is held in a storage array which allows data to be written a line of 8n bits at a time, but to be read selectively in sequences of 2n bits. Thus, according to the described embodiment there is an input data port for writing of 128 bits and four output data ports for reading, each of 32 bits. Thus, lines of 128 bits in length are written one at a time, while it is possible to read different numbers of 32 bit sequences depending on the instruction mode of the machine.
According to a first instruction mode, one sequence of 2n-bits is read out during each machine cycle to supply a pair of n-bit instructions to a decode unit (referred to herein as GP16 mode).
According to a second instruction mode, two sequences of 2n-bits are read during each machine cycle to provide two 2n-bit instructions to the decode unit (referred to herein as GP32 mode).
According to a third instruction mode, four sequences of 2n-bits are read out during each machine cycle to provide simultaneously four instructions each of 2n-bits to the decode unit (referred to herein as VLIW (Very Long Instruction Word) mode). It is a function of VLIW mode that these four instructions constitute the line held in the storage array.
The present inventors have developed a storage array which supports these instruction modes in a simplified fashion.
According to the present invention there is provided a storage array for holding instructions in a processor comprising:
a first set of storage cells each having a write input and a single read output;
second and third sets of storage cells each having a write input and only two read outputs; and
a fourth set of storage cells each having a write input and only three outputs,
wherein all the write inputs are addressable in common by a single write address and wherein the read outputs are individually selectable responsive to a read pointer.
In the described embodiment, the storage array comprises four output ports, wherein the first output port is connected to receive data from any of the first to fourth sets, the second output port is connected to receive data only from the second or fourth set, and the third and fourth output ports are connected to receive data respectively only from the third and fourth sets.
The storage array can include read circuitry for reading instructions out of the storage array in dependence on the instruction mode of the processor. Thus, according to the first instruction mode the read circuitry reads out successively from the first to third sets during successive machine cycles to supply a pair of instructions to the first output port during each machine cycle.
In the second instruction mode, the read circuitry reads out from the first and second sets during a first machine cycle and the third and fourth sets during a next machine cycle to provide two instructions respectively to the first and second output ports during each machine cycle.
According to the third instruction mode, the read circuitry read out all four sets during each machine cycle to provide the four VLIW instructions respectively to the first to fourth ports.
By carefully arranging the configuration of the storage array as defined above to support the three instruction modes, it has been possible to significantly reduce the routing congestion of hard-wires, because all sets of storage cells do not need to be connected to every output port. That is, it removes the requirement for each memory cell to have four read ports, which would normally be the case if the memory cell was for connection to four output ports. Reducing the number of read ports for each cell makes routing easier and saves silicon area.
In addition, the read circuitry can be simplified and can be provided by a number of reduced input multiplexor gates as outlined in the following description.